Volume 11 - Volume 11
Design of High-Speed Low Power Computational Blocks for DSP Processors
Abstract
In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power
optimization and speed play a very important role. This importance for low power has initiated the
designs where power dissipation is equally important as performance and area. Power reduction
and power management are the key challenges in the design of circuits down to 100nm. For power
optimization, there are several techniques and extension designs are applied in the literature. In
real time Digital Signal Processing applications, multiplication and accumulation are significant
operations. The primary performance criteria for these signal processing operations are speed and
power consumption. To lower the power consumption, there are techniques like Multi threshold
(Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used
which allows reduction in power, delay and area of digital circuits, while maintaining low
complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder,
Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and
compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in
terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The
Simulation results shows that GDI based designs consume less power and delay also reduced
compared to CMOS based designs.
Paper Details
PaperID: 1768
Author's Name: N. Alivelu Manga, V.V. Satyanarayana Tallapragada, G.V. Pradeep Kumar and R. Sai Prasad Goud
Volume: Volume 11
Issues: Volume 11
Keywords: VLSI, CMOS, Gate Diffusion Input (GDI), Braun Multiplier, Parallel-Prefix Adder.
Year: 2021
Month: April
Pages: 1419-1429