Volume 11 - Volume 11
Design of High Speed and Low Area Confined Multiplier on FPGA
Abstract
In this Advanced world, Technology is playing the major role. Most importantly development in
Electronics field has a large impact on the improved life style. Among the advanced applications,
DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital
Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for
the performance of the device. Using RTL simulation and a Field Programmable Gate Array
(FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single
bit adders are removed and replaced with multiplexers in this project. So that the less often used
FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture
results in significant reductions in FPGA resources, latency, area, and power. These multiplication
approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE
14.7. Finally, the Spartan 3E FPGA is used to implement the design.
Paper Details
PaperID: 2315
Author's Name: Kandagatla Ravi Kumar, Cheeli Priyadarshini, Kanakam Bhavani, Ankam Varun Sundar Kumar and Palanki Naga Nanda Sai
Volume: Volume 11
Issues: Volume 11
Keywords: FPGA, Multiplier, Xilinx, CSLA.
Year: 2021
Month: July
Pages: 2736-2746